GSys LibreCore — a source-available RISC-V core and agentic build platform, derived from OpenHW CVA6. Explore the layered architecture.
CPU CoreHypervisor & Sstc

Hypervisor & Sstc

GSys LibreCore implements the RISC-V Hypervisor (H) extension surface under RVH / HExtEn, plus Sstc guest timers (vstimecmp, henvcfg.STCE) for KVM-oriented hosts. Default shipping packages keep H off; server packages opt in.

Authority: architecture/server-math-hypervisor.md, architecture/remaining-upgrade-sequence.md. Spec: Priv II hypervisor chapter, Sstc.

Product status (summary)

TrackMeaning
U9.0 Sstc × Hvstimecmp / vstimecmph, henvcfg.STCE, VS alias of stimecmp, hardwired mip.VSTIP when STCE pair set
U9.1 Guest time offsethtimedelta / htimedeltah; guest time = mtime + htimedelta; multi-context PLIC
U9.2 Trap polishVirtual-instr on STCE fail under V; HVIP vs hardwired VSTIP; VS entry litmus
G-stageTwo-stage + G-only walks present in PTW; full KVM stress still operator-owned
HFENCE / HLV / HSVDecoder + commit / MMU flush / load-store FU paths when H on
hgeie / hgeipStub (always 0) — multi-guest external interrupt IDs not a product claim yet

check_cfg treats SstcEn && RVH as legal (required pair for guest timer story).

CSR / microarch seats

FeatureTypical locus
vstimecmp, htimedelta, HS CSRscore/csr_regfile.sv
G-stage PTWcore/cva6_mmu/ / cva6_ptw.sv
HFENCEDecoder + commit + MMU flush
HLV/HSVDecoder → load/store FU
PLIC multi-contextcorev_apu/rv_plic + harness fan-out

Enable packages

PackageH / SstcNotes
Default cv64a6_imafdc_sv39 etc.Usually offIdentity host
g6lc64_server_mathOnH+Sstc + math stack; RVV off
g6lc64_server_math_vOnSame + RVV when Ara linked
g6lc64_stream8OnH+Sstc in-order stream bring-up (NrCores=2)
g6lc64_aiOnSame envelope + SI island
g6lc64_smt2_ooo_intSstc onlySMT2-over-OoO production; RVH off
g6lc64_ooo_serverCheck packageWide OoO host — opt-in / unqualified (drained FP legal since M4; COH_FILTERED leg without evidence)

Confirm bits in the package source before marketing a KVM target.

Best-practice bring-up

  1. Single-core server package with H+Sstc — guest timer litmus (verif/tests/custom/sstc_h/…).
  2. Raise NrCores + L2 for SMP host.
  3. Bring up OpenSBI + Linux as a hypervisor host (external to this page).
  4. Only then compose SMT or Ara if needed — each multiplies debug space.

Verification

g6lc-build verify --target g6lc64_server_math
g6lc-build test --suite server-math-tests   # optional

Directed: vstimecmp / htimedelta assembly under verif/tests/custom/sstc_h/. Full KVM regression is lab / residual, not default verify.

Software / DTS

  • misa.H (and related ISA string tokens) must match package
  • Sstc discovery for supervisor/guest timer software
  • PLIC contexts sized for multi-core M/S
  • See AGENTS-dts-validation.md when changing timer or interrupt topology

Related

SMTVector & Ara