GSys LibreCore — a source-available RISC-V core and agentic build platform, derived from OpenHW CVA6. Explore the layered architecture.
CPU CoreServer Profiles

Server Profiles

“Server” on this project means Linux-class configs that compose multi-issue or OoO, optional SMT, L2/L3, hypervisor timer extensions, and math/memory acceleration — always through named config packages, never ad hoc RTL forks.

Detail: architecture/remaining-upgrade-sequence.md, architecture/server-math-hypervisor.md, architecture/ara-vector-attach.md.

Package families (illustrative)

Confirm exact filenames under core/include/.

FamilyIntentTypical stack
g6lc64_ooo_intOoO bring-up baselineOoOEn, integer-only, NrHarts=1, NrCores=1
g6lc64_smt2_ooo_intProduction SMT2 over OoOOoOEn, integer-only, NrHarts=2, mixed residency (M2), ring 16, WT D$, eWT L2
g6lc64_ooo_int2OoO coherence integration (integer anchor)drained handoff + NrCores=2, COH_OOO, signature snoop filter, eWT L2, four-hart strict boot
g6lc64_ooo_int2_l3OoO + L3 performance packageooo_int2 + non-inclusive 1 MiB L3 (SRAM tags), RV64GC+B (M4), ring 16, CohMaxOutstanding=8
g6lc64_oooDual-issue OoO liteOoOEn + FP — legal single-hart FP since M4 (bring-up, no boot evidence)
g6lc64_ooo_serverServer OoOWide issue, multi-core×hart, L2/L3 auto, memdep — opt-in / unqualified (drained FP legal; COH_FILTERED leg without evidence)
g6lc64_smt2Dual-threadNrHarts=2, hybrid switch, in-order, often L2
g6lc64_server_mathKVM / math host (C-light)H+Sstc, RVB, Zicbo*, HWPF, HPDCACHE, L2 auto; RVV off until Ara
g6lc64_server_math_v+ RVVVExtEn, Ara attach; CvxifEn exclusive with accelerator path
g6lc64_stream8Stream8-class bring-upIn-order, NrCores=2, H+Sstc, Zacas W/D/Q
g6lc64_stream8_l3, g6lc64_server_math_l3In-order two-core + L3 (M6)HPDCACHE_WT, COH_FILTERED, non-inclusive 1 MiB L3, eWT L2; strict two-core OpenSBI boots
g6lc64_aiSI islandstream8 envelope + Xg6lcai / ai_island
g6lc64_smt2_aiSMT2 + SI islandsmt2 envelope (2 harts, dual issue) + Xg6lcai / ai_island, per-hart accumulator banks

Default packages (e.g. cv64a6_imafdc_sv39) remain the identity path for integrators who want classic CVA6 behavior.

Composition rules

  1. Config package is the product SKU. Selecting a package sets dozens of knobs consistently (check_cfg enforces legality).
  2. L2/L3 live in APU, not as L1 hacks — see L2 / L3 Cache.
  3. H + Sstc before heavy guest timer work; G-stage present, KVM stress still operator-owned.
  4. Ara / RVV prefers the CVXIF / acc_dispatcher seam; CvxifEn and accelerator enables are mutually exclusive by assertion.
  5. SMT × KVM is a later composition — bring up SMT bare-metal first.

Operator selection

# .config.ts
export default defineBuildConfig({
  soc: { coreConfig: 'g6lc64_server_math' }, // example
})
 
g6lc-build config
g6lc-build verify --target g6lc64_server_math

Board selection (g6lc-build mb select) may pin soc.* via overlay — do not fight the board contract when co-developing FPGA targets.

Software / DTS

CapabilityVisibility
ISA string / misaMust match package extensions
Multi-hart / SMTMultiple cpu@ nodes, CLINT/PLIC sizing
L2/L3next-level-cache / cache nodes when present
HypervisorOpenSBI + Linux KVM prerequisites

Cross-check: AGENTS-dts-validation.md and build-platform/scripts/validate-cva6-dts.*.

Related product pages

Vector & AraAgent Workflow