SI Island (Xg6lcai)
The super-intelligence (SI) plane has two halves on two sides of the core boundary (the plane split of
architecture/ai-matrix/scaling-100tops.md §3):
| Plane | Where | What | Reached by |
|---|---|---|---|
| T0 / T1 core-attached | core/cvxif_g6lc_ai/ on the CVXIF seam (seam B) | fixed 8×8×8 INT8 tile unit (ai.dot4, ai.mma, tile moves, requant), SI CSRs, per-hart accumulator banks | custom-2 instructions, precise traps |
| T2 island | corev_apu/ai_island/ — a device on the fabric | the GEMM sequencer (g6lc_ai_gemm_seq), banked tc_sram operand/result tiles, descriptor engine, queues, completion FIFO, capability window | descriptor rings, doorbell / ai.enq, ai.poll, PLIC IRQ |
Normative text lives in the monorepo scaffold, not here:
architecture/ai-matrix/isa-encoding.md (opcodes, CSR, descriptor), numeric-formats-datapath.md,
va-turbo.md, scaling-100tops.md, corev_apu/ai_island/README.md (live MMIO map) and the
running log architecture/ai-matrix/log-2026-09.md. This page is the map and the current state.
Evidence classes (read before any number)
Every figure in the SI record carries one of four labels, and they are never mixed:
| Label | Source | Example |
|---|---|---|
| measured | Verilator SoC model of the built geometry (cycles, not timing) or the 8-lane backend bench | 1×512×512 INT8 cold 34,136 cycles, resident 590 |
| derived | a model calibrated from measured per-beat / per-issue costs | the V1..V4 ladder table (ai_bench_report.py --sku) |
| projected | a nameplate from a config literal | 98.3 TOPS for AiIslandV4Octo |
| virtual | the QEMU contract emulator or the software reference backend | B1 boot + queue smoke, diffusion PSNR |
A QEMU or software-reference result is never RTL or silicon evidence.
The live island (g6lc64_ai, 2026-09-30)
| Property | Value | Status |
|---|---|---|
| MAC issue | 512 lanes × 1 output column per cycle | measured (2.048 TOPS nameplate at 2 GHz) |
| Port | 64-bit AXI, 8 B/cycle → machine balance 64 MAC/byte | measured: B stream at 1.002–1.008 cycles/beat |
| Formats | INT8, INT4, FP8 E4M3/E5M2, FP16, BF16, FP32 (grant 0x00FB; SP24 refused) | FP island is the shipped package since 2026-09-30 (IslandFpEn=1) |
| Operand banks | flat-panel mapping, byte-capacity box: A 2 MiB, B 1 MiB, C 2 MiB | measured: 1×256×1024 INT8 is one job, one resident key |
| Sequencer box | M ≤ 1024, N ≤ 512, K by bank bytes (CAP_OFF_BANK_A/B_BYTES) | published in the capability window |
| VA-Turbo residency | two-slot resident-B directory, resident-A key (VaTurboEn, off in production) | measured on the bench SKU: 1×768×512 two panels both hit, 39×; intra-row trail store 846 → 590 |
| C store | 8-byte pairs on the 64-bit port; wide C store (DataWidth/32 columns per beat) when rows are beat-aligned | 64-bit path cycle-identical (226/226); 128/512-bit paths verified on tb_g6lc_ai_gemm_wide (one 64 B beat for 16 columns) |
| Accumulate mode | CAP_OFF_ACCMODE bit 0, K-split chains through C | measured (+2.2 % seed cost per block) |
| Area (island, reduced review fixture) | 11,896 generic cells, 8,234 FF, $div 0, no SCC | yosys generic, not timing |
Bottleneck ledger (measured)
- A1 decode (m = 1) is bytes-bound by construction: cold
1×512×512INT8 runs at 7.7 MAC/cycle (1.5 % of peak) because the weight panel streams once at 8 B/cycle. Only bytes/cycle (port width, channels) and bytes (formats, residency) move it. Resident decode reaches 87 % MAC efficiency. - A2 prefill (m ≫ 1) is MAC-bound at the single output column per cycle → the column array (V2).
- The C store was the next floor once columns > 2 at short K → the wide C store (landed).
- T0 ops (
dot44.07 cycles/op loop-inclusive) are control plane, not a throughput lever.
Scaling ladder toward 100 TOPS (balanced: memory before MACs)
Four SKU literals in g6lc_ai_island_cfg_pkg (AiIslandV1WidePort, V2ColumnArray, V3Quad,
V4Octo); tb_g6lc_ai_scale_ladder pins legality and nameplates, ai_bench_report.py --sku
prints the derived table, suite ai-scale-ladder runs the local evidence in minutes.
| Step | Axis | Nameplate | RTL state |
|---|---|---|---|
| live | 1 × 512 MAC, 8 B/cycle | 2.05 TOPS, balance 64 | shipped |
| V1 wide port | 512-bit island port + class-0 channel (64 B/cycle), 64-bit cluster upsized in g6lc_ai_dram_join | 2.05 TOPS, balance 8 | plumbing landed; leaf: join + slave at 1.00 cycles/beat, the island’s own B stream at 60.4 B/cycle on the V1 shape (7.5× the narrow path); SoC point not yet measured (harness preload defect for 8-cut SRAM words fixed, AI_START trace added, run queued) |
| V2 column array | OutCols = 8 dot units share one A word, B banked by column group, wide C store | 16.4 TOPS @ 2 GHz | RTL landed: OutCols=1 cycle-identical, OutCols 2/4 pass every directed case; island gate strict lint 0; FP32 16×16×16 MAC phase 2064 → 528 at 4 columns; wide store lands 16 columns per 64 B beat |
| V3 quad / V4 octo | g6lc_ai_cluster_dispatch: N engines split one job along N (per-slice ptr_b/ptr_c, ldc = n), axi_mux with cluster-prefixed IDs, one master; the island top elaborates it for Clusters > 1 | 49.2 / 98.3 TOPS @ 1.5 GHz | RTL landed, leaf-verified: 2- and 4-cluster C bit-identical to the single engine (m2 n32 k16 241 → 191 cycles); island top elaborates Clusters 1/2/4 at reduced geometry; not synthesized at full geometry, no SoC point |
The batch-1 trap (scaling note §5) still holds: decode needs bytes, not TOPS; the ladder’s 100-TOPS end is the prefill / batched / conv regime.
Verification ladder for the island
Left to right is where a violation is caught first:
- Package arithmetic + legality —
island_cfg_legal,check_cfg(grant ⊆ implemented, FP plane needs RVF/RVD). - Bounded formal —
corev_apu/ai_island/formal/g6lc_ai_gemm_flat.sby: flat-panel pitch/capacity, row disjointness, burst length, DRAM stripe cap, resident-slot placement over the pure functions the sequencer calls (three geometries; a pitch mutation fails). Wired intoverify --formal. - Run-time contracts — C1–C4 in
g6lc_ai_gemm_seq(bank bounds, no stripe-crossing bursts, trail store reads only written pairs). - Directed minis + the 8-lane backend bench —
verif/regress/ai-ops-bench.sh(63 s locally, 226 records, seven formats, both float pipes; cycle-identity is the regression gate for every refactor). - SoC directed suite + bench matrix —
ai-matrix-veri.shwith oracle controls (ai_must_pass/ai_must_fail; a misclassified control voids the run),ai_bench_gemm.Sper format/shape/path/residency,+ai_pmu_traceAI_JOBrecords. - QEMU contract emulator (
g6lc_qemu, B1) — descriptor/queue/capability contract, boots OpenSBI; never an RTL number.
Host software: ai-tensor
ai-tensor/ is the project-independent host backend (PyTorch first, TensorFlow second): one 64-byte
descriptor ABI for MMIO doorbell, ai.enq, and the frameworks; a mandatory software-reference/sim
backend; hardware backends feature-gated; a pinned cross-connect to the island ABI.
AiTensorLinear/AiTensorConv2dlower to island jobs and take the largest K the banks admit (Caps.bank_*_bytes); K beyond the banks chains through accumulate mode.- Qualification tools with retained records under
fixtures/qual/:qualify_llm.py(distilgpt2: INT8 g128 + FP16 head selected at 0.369× FP32 bytes) andqualify_diffusion.py(tiny-sd ladder; pretrainedsegmind/tiny-sd: INT8 g64 35.0 dB PASS, g128 30.7 dB FAIL retained, BF16 48.5 dB). Virtual evidence. ai_tensor.cost_model: a derived island cost model calibrated on the measured SoC points (1×512×512cold/resident, FP321×256×1024), bytes- vs MAC-bound classification, offload-vs-host decision, and the archetype recipe table (A1/A2 decode-prefill, A3 conv, A4 K-chain) filtered by the capability grant.
SMT2 + SI
g6lc64_smt2_ai (two software harts, dual issue, SI island, per-hart accumulator banks) exists because
the SI plane is meant to be driven by several software threads with per-hart SI CSR banks and SoC-isolated
queues. check_cfg retired the CvxifEn && NrIssuePorts > 1 ban in favour of the issue-stage port-0
steering contract (asserted in issue_read_operands, exercised by mini_ai_dual_issue.S). State: the SoC
builds, oracle controls behave, and ai_dot4_s8_smoke, ai_mma_s8_golden, ai_queue_doorbell,
ai_island_mmio_smoke pass on the two-hart dual-issue model. Queued: the dual-issue mini rerun, the two-hart
boot-load bench (ai_bench_smt2.S, per-hart queues), the strict OpenSBI boot (ariane-smt2-ai.dts).
Island on any configuration (2026-10-01)
| Item | State | Evidence |
|---|---|---|
| Enable on any package | +define+G6LC_AI_OVERLAY[_INT] (build_config splices config_pkg::AiCfgIsland); pinned <pkg>_ai packages + DTS from ai-overlay pin (g6lc64_ooo_int2_l3_ai, g6lc64_stream8_l3_ai, g6lc64_smt2_ooo_int_ai); +define+G6LC_AI_ISLAND_CFG=<literal> for the geometry | verify --lint --ai-overlay adds no error on six targets; SoC-top Verilator lint clean on the three pins; drift test in bun test |
| Coherent outputs | AiCfg.DmaInvalEn (CAP 0xA0 bit 0): each completed island write is invalidated through the CMO engine’s writer port after its B, per 64 B line, and a job’s completion is held until its invalidations returned; cbo.inval remains the software fallback | leaf tb_g6lc_ai_inval_queue + mutation PASS; SoC ai_coh_stale/_sw in the suite, not yet run; cost unmeasured |
| Every core enqueues | g6lc_ai_enq_arb (round-robin) in the cluster; the island allocates the ticket stream (SbTicketAlloc) | leaf + mutation PASS; SoC ai_mc_enq not yet run |
| OoO cores | CVXIF issues only at the commit head (g6lc_iq), so the coprocessor’s issue-time side effects are never speculative | leaf tb_g6lc_iq_cvxif_head + mutation PASS; SI subset on g6lc64_ooo_int2_l3_ai not yet run |
| FP island on integer cores | IslandFpEn no longer requires RVF/RVD (T0 float grants still do) | g6lc64_smt2_ooo_int_ai elaborates with the FP island |
| Two-hart boot-load bench | HARTS=1 control: 4 decode jobs, 135,931 wall cycles (33,872 each) on g6lc64_smt2_ai; HARTS=2 failed on an ELF defect (queue-1 region), fixed, rerun owed | ai-chain10 |
Open items (as of 2026-10-01, end of pass)
- V1 SoC measurement (queued with the
AI_STARTtrace; island and memory path proven on leaves). - Full-geometry synthesis of a cluster SKU and its SoC gate; derived-table refresh.
- Cross-job B prefetch (WP5): designed — needs a second B-load context to overlap the next job’s panel load with the current MAC.
- Strict OpenSBI boot on
g6lc64_smt2_ai(admitted in the runner; ~24 h at the FP-island model’s speed). - Serialized rerun of the FP-island directed suite and seven-format cold points (the 2026-10-01 run is void: pre-fix tree snapshot); 512-lane FP synthesis anchor (runner error, rerun owed).
- SoC runs of
ai_coh_stale/ai_coh_stale_sw,ai_mc_enqand the SI subset ong6lc64_ooo_int2_l3_ai; DMA-invalidation cost (budget < 2 % cold, < 5 % resident); two-hart benchHARTS=2rerun; the sidebandai.enqhang seen once ong6lc64_smt2_ai.
Playbooks: the AI section of AGENTS-todo.md, architecture/ai-matrix/README.md,
ai-tensor/AGENTS.md, g6lc_qemu/AGENTS.md.